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triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 1 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. 9.9-12.5gb/s optical modulator driv er TGA8652-EPU-SL oc-192 metro and long haul applications surface mount package key features and performance ? dc - 12 ghz linear bw ? dc - 16 ghz saturated power bw ? 16 db small signal gain ? wide drive range (4v to 8v) ? 25 ps edge rates (10/90) ? low power dissipation (1.4w at vo=8v) ? package size: .350 x .350 x .084 inches. ? evaluation board available. primary applications ? mach-zehnder modulator driver ? pre-driver ? receiver agc description the triquint tga8652-epu is a medium power wideband agc amplifier combined with off chip circuitry assembled in a surface mount package. the tga8652-epu typically provides 16db small signal gain with 6db agc range. typical input and output return loss is <10db. typical noise figure is 2.5db at 3ghz. typical saturated output power is 25dbm. small signal 3db bw is 12ghz with saturated power performance to 16ghz. rf ports are dc coupled enabling the user to customize system corner frequencies. applications include oc192 12.5gbit/s nrz mz modulator driver and receive agc amplifier. drain bias may be applied thru the on-chip drain termination resistor for low drive applications or thru the rf output port for high drive applications. a cascaded pair demonstrated 8vpp output voltage swing with 500mvpp at the input when stimulated with 10gbit/s. 2^31-1prbs. nrz data. the tga8652-epu is available on an evaluation board. cascaded 8652 evaluation boards 12.5 gb/s performance output = 8 vpp, input = 500 mvpp scale: 2 v/div, 20 ps/div measured performance
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 2 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. symbol parameter 1/ value notes v + vd(rfout) positive supply voltage drain bias applied thru on-chip termination drain bias applied at rf output using bias t 12 v 10 v v + id positive supply current drain bias applied thru on-chip termination drain bias applied at rf output using bias t 110 ma 250 ma 2/ p d power dissipation 2.4 w 3/ vg ig negative gate voltage gate current 0 v to ?3 v 5 ma vctrl ictrl control gate voltage gate current vd/2 to ?3 v 5 ma 4/ p in rf input sinusoidal continuous wave power 23 dbm t ch operating channel temperature 150 0 c5/ 6/ t stg storage temperature -40 to 125 0 c notes: 1/ these ratings represent the maximum operable values for the device. 2 / assure the combination of vd and id does not exceed maximum power dissipation rating. 3 / when operated at this bias condition with a base plate temperature of 80 0 c, the mean time to failure (mttf) is reduced from 2.6e+7 to 1e+6 hours. 4 / assure vctrl never exceeds vd during bias on and off sequences, and normal operation. 5 / these ratings apply to each individual fet. 6 / junction operating temperature will directly affect the device median time to failure (m ttf). for maximum life, it is recommended that junction temperatures be maintained at the lowest possible levels. maximum ratings
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 3 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. thermal information* parameter test condition t ch ( c) r jc ( c/w) mttf (hrs) r jc thermal resistance (channel to backside of package) vd(rf out) = 6.5 v, vctrl = 1 v, id = 170 ma 5%, t base = 80 c 114.70 31.40 2.6e+7 note: thermal transfer is conducted thru the bottom of the tga8652-epu package into the motherboard. design the motherboard to assure adequate thermal transfer to the base plate. an array of filled thermal vias is recommended as shown in the example below. * this information is a result of a thermal model. thermal vias in motherboard area of thermal transfer bottom view tga8652-epu motherboard
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 4 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. rf specifications (t a = 25 c nominal) value note test measurement conditions min typ max units small signal bw 12 ghz saturated power bw 16 ghz 1/, 2 / small-signal gain magnitude 2 and 4 ghz 6 ghz 10 ghz 14 ghz 16 ghz 15 13 13 10 10 16 15 14 13 13 db small signal agc range midband 15 db 1/, 2 / input return loss magnitude 2, 4, 6, and 10 ghz 14 and 18 ghz 9 8 10 10 db 1/, 2 / output return loss magnitude 2, 4, 6, and 10 ghz 14 and 18 ghz 10 8 10 10 db 6/, 7 / saturated output power 2, 4, 6, 8, and 10 ghz 25 dbm 3/, 4 / eye amplitude vd (rfout) = 7 v vd (rfout) = 6 v vd (rfout) = 5 v vd (rfout) = 4.5 v 8.0 7.0 6.0 5.5 vpp 3/, 4 /, 5 / additive jitter (p-p) 5 ps 3/, 4 / rise time (10/90) 25 ps notes: 1 / verified at package level rf probe. 2 / package probe bias: v + = 8 v, adjust vg1 to achieve id = 87 ma, vctrl = +1 v 3 / verified by design, tga8652epu assembled onto a demonstration board shown on page 7 then tested using the application circuit and bias procedure detailed on pages 8 and 9. 4 / vin = 2 v, data rate = 12.5 gb/s, vctr l and vg are adjusted for maximum output. 5 / computed using rss method where jpp_additive = sqrt(jpp_out 2 - jpp_in 2 ) 6 / verified at die level on-wafer probe. 7 / power bias die probe: vdt=8 v, adjust vg to achieve id = 175 ma+/-5%, vctrl = 1.5 v note: at the die level, drain bias is applied thru the rf output port using a bias tee, voltage is at the dc input to the bias tee.
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 5 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. -35 -30 -25 -20 -15 -10 -5 0 012345678910111213141516 frequency (ghz) retur n los s (d b) 0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 6 7 8 9 10 111213141516 fre quency (ghz ) gain (db) typical measured s-parameters irl orl gain
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 6 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. vg vctrl rf(in) rf(out) demonstration board v +
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 7 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. 12 rf(in) vd(rfout) vg vctrl tga8652 vdt application circuit for 4-8v driver application bias tee (pspl 5542) 11 9 6 3 rf(out) v + (no connection) dc block (pspl 5509) c1 c3 c4 c5 c2 designator description manufacturer part number c1, c3 1uf capacitor mlc ceramic avx 0603yc105kat c2, c4 10 uf capacitor mlc ceramic avx 0603yc106kat c5 0.01 uf capacitor mlc avx 0603yc103kat recommended components:
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 8 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. bias on 1. disable the ppg source 2. set vdt = 0v vctrl = 0v and vg = 0v 3. set vg =-1.5 v 4. increase vdt to 8v observing id. - assure id = 0ma 5. set vctrl = +1.0 v - id should still be 0 ma 6. make vg more positive until idd = 175ma . - typical value for vg is -0.3 v 7. enable the ppg source - vin = 2 vpp 8. adjust vctrl for vo = 8vpp 9. adjust vg for 50% crossover bias off 1. disable the output of the ppg 2. set vctrl = 0v 3. set vdt = 0v 4. set vg = 0v bias procedure for 4-8v driver application notes: 1. assure vctrl never exceeds vd during bias on and bias off sequences and during normal operation.
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 9 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. typical measured performance on demonstration board 12.5gb/s 2^31-1, vd(rfout) = 7 v cpc = 50% vo=8 v vo=7 v vo=6 v vo=5 v vo = 4 v
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 10 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. typical bias conditions vd(rfout) = 7 v notes: 1. vd(rfout)=7 v 2. vin =2 vpp 3. 50% cpc 4. actual bias points may be different. vo(v) 8 7 6 5 4 vg(v) -0.23 -0.31 -0.40 -0.48 -0.54 id(ma) 194 173 144 117 97 vctrl 0.87 0.63 0.37 0.16 0.02
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 11 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. 12 rf(in) vd(rfout) vg vctrl tga8652 application circuit for pre-driver and receive application 11 9 6 3 rf(out) v + dc block (pspl 5509) c1 c3 c4 c5 c2 designator description manufacturer part number c1, c3 1uf capacitor mlc ceramic avx 0603yc105kat c2, c4 10 uf capacitor mlc ceramic avx 0603yc106kat c5 0.01 uf capacitor mlc avx 0603yc103kat recommended components: dc block (pspl 5509)
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 12 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. bias on 1. disable the ppg source 2. set v + = 0 v, vctrl = 0 v and vg = 0 v 3. set vg = -1.5 v, set vctrl = -0.1v 4. increase v + to 8 v observing id. - assure id = 0 ma 5. make vg more positive until idd = 70 ma . - typical value for vg is -0.5 v 7. enable the ppg source - set vin = 500 mv (amplitude) bias off 1. disable the output of the ppg 2. set vctrl = 0v 3. set vdt = 0v 4. set vg = 0v bias procedure for pre-driver and receive application notes: 1. assure vctrl never exceeds vd during bias on and bias off sequences and during normal operation.
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 13 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. mechanical drawing notes: 1. dimensions: inches. tolerance: length and width: +/-.003 inches. height +/-.006 inches. adjacent pad to pad spacing: +/- .0002 inches. pad size: +/- .001 inches. 2. surface mount interface: material: ro4003 (thickness=.008 inches), 1/2oz copper (thickness=.0007 inches) plating finish: 100-350 microinches nickel underplate, with 5-10 microinches flash gold overplate.
triquint semiconductor texas: (972)994 8465 fax (972)994 8504 email: info-mmw@tqs.c om web: www.triquint.com product data sheet june 14, 2005 14 note: devices designated as epu are typically early in their characterization process prior to finalizing all electrical and pr ocess specifications. specifications are subject to change without notice. assembly of a tga8652-epu surface mount package onto a motherboard manual assembly for prototypes 1. clean the motherboard with acetone and rinse with alcohol and di water. allow the motherboard to fully dry. 2. using a standard sn63 solder paste, such as kester sn63 r-560, dispense solder paste dots of 5 to 15 mil in diameter to the motherboard as shown in the example motherboard in figure 1 below. assure that there is a minimum of 5 mils and a maximum of 1 0 mils between the edge of each solder paste area and the closest edge of the ground pad. 3. manually place a tga8652-epu on the motherboard with correct orientation and good alignment. the alignment can be determined manually by centering the package on the motherboard. the rf trac es (pin 6 and pin 12) are located along the center horizontal axis of the package. dc traces pin 3 and pin 9 are located along the center vertical axis of the package. (fig. 2) 4. reflow the assembly on a hot plate with the surface temperature of the plate near 230 o c for 5 to 6 seconds. 5. let the assembly completely cool down. this package has little or no tendency to self- align during the reflow . 6. clean the assembly with acetone and rinse with alcohol and di water. high volume assembly of the package the tga8652-epu is a standard surface mount component compatible with standard high volume assembly processes using standard sn63 solder paste, such as kester r560. refer to kester r560 manufacture data sheet for recommended reflow profile, cleaning, and handling. dispense solder paste usi ng standard solder printing techniques such as stencil solder printing. pick-and-place using a standard machine such as mrsi machine. perform solder reflow using a sikama reflow system. recommended solder stencil and motherboard interface layout are available upon request. solder paste dispensing areas (19 plcs) figure 1: solder paste dispensing pattern used on the evaluation board motherboard. figure 2: bottom view [tga8652-epu] pin 1 pin 1 pin 12 rf(in) caution: the tga8652-epu contains gaas mmic devices are susceptible to damage from electrostatic discharge. proper precautions should be observed during handling, assembly and test.

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